(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes related to the chemical-mechanical-planarization of semiconductor wafers.
(2) Description of Prior Art
The fabrication of integrated circuits not only involves the forming of semiconductor devices within the surface of a semiconductor wafer but also the creation of a complex network of wiring interconnections which comprise the electrical circuitry of the completed chip. These interconnections are accomplished by the alternate deposition of thin layers of conductive and insulating materials over the semiconductor devices. Each conductive layer is patterned by photolithographic techniques to form the wiring design for that level. This patterning process produces a surface with topological features, which, if no steps were taken, would replicate itself in each succeeding layer.
Conductive layers are usually metals such as aluminum, are deposited by physical-vapor-deposition(PVD) techniques such as vacuum evaporation or sputtering. These methods do not provide conformal coverage and the presence of topological features on the surface onto which they are deposited result in non-uniformities in thickness and other problems related to the shadowing effects of non-planar surfaces.
Frequently two to four levels of interconnection metallurgy are required to form the required circuits. In order to provide a planar surface for each level of metal, various methods have been used to planarize the insulator surface. Glasses which flow when heated are commonly used to accommodate the first layer of metallization. Subsequent levels where elevated temperatures are no longer permissible, employ layers of materials which are deposited as liquids and then cured to form solid layers. Such layers of spin-on-glasses and organic polymers provide an improved local surface planarity. Subsequent reactive-ion-etching(RIE) removes the polymers and translates the new surface to the insulating layer.
Although these methods can provide great refinement to local planarization, they cannot provide planarization over a large area. This is because the integrated circuit chips themselves contain discrete regions of different topological complexity such as memory arrays located within regions of logic circuits.
Recent years have seen an increased interest in adapting the technique which is used to provide the wafer with a planar surface in the first place--chemical-mechanical-polishing(CMP). At first thought, a seemingly crude method for dealing with dimensions of the order of hundredths of a micron, the technique has been refined and utilized with much success in recent years.
One of the difficulties with this method is the monitoring of its progress and the determination of when the polishing process should be terminated. In general, the tool used for CMP consists of a large circular rotatable platen fitted with a soft pad onto which a slurry of fine particles and a chemical etchant is continuously applied. The wafer being polished or planarized is mounted up-side down on a smaller rotating disk which places it in contact and under controlled pressure with the polishing pad of the platen.
Periodic calibration of polishing rates using monitor wafers is not practical with CMP. Because of polishing pad wear the polishing rates are time dependent as is shown by the declining removal rate RR with wafer count in FIG. 1. Each wafer should have its film thickness measured periodically during the CMP process and instantaneous removal rates determined to avoid over-polishing. This seemingly tedious procedure is rewarded by the elimination of ruined wafers and the avoidance of re-work.
True in-situ observation of the surface of the wafer under these conditions is possible only if the large polishing table is fitted the observation device itself or with an opening through which the observation device may operate. Such observations typically require extensive calibration and employ indirect means for determining the desired monitoring parameter. By and large, true in-situ methods focus attention on a single wafer site only. Generally, these methods, which measure capacitive or conductive changes, require elaborate calibration and do not have the sensitivity which optical thickness measurements can provide.
Non in-situ techniques require polishing for a period of time over the polishing platen, moving the wafer assembly to a measurement station, measuring the remaining layer thickness or degree of planarity, and then returning the wafer assembly to the polishing platen. Such monitoring techniques, although disruptive of the polishing process and non-periodic, have advantages which make them uniquely practical in some instances.
Burke et.al. U.S. Pat. No. 5,492,594 describes an apparatus with a separate measurement station wherein the wafer carrier is mounted on a moveable support arm which can rotate the assembly from the polishing position over the rotating platen to a measurement position over a plurality of electrodes contained in an electrolyte. The capacitance of the dielectric layer is measure and associated with the thickness of the dielectric layer. This method requires careful calibration and does not make a direct thickness measurement at a discrete location.
Other techniques which may be called "quasi" in-situ make use of periodic off-table excursions of the rotating wafer carrier head. These excursions are part of a linear travel of the wafer carrier head along the radius of the polishing platen during normal operation. When the carrier travels part way off the polishing platen the wafer surface is exposed and a measurement can be made. Such measurements are periodic and sufficiently frequent to provide useful monitoring capability.
One such a technique is described by Koos et.al., U.S. Pat. No. 5,413,941. Here the wafer being polished is faced against a mirror as it comes off-platen. Laser light is passed transversely between the wafer surface and the mirror, causing multiple reflections between mirror and wafer. A detector at the opposite side records the linear intensity signature of the wafer surface from the exit beam. This signal is a direct measure of the degree of surface planarity and as such provides an excellent monitor of the planarization process. The Koos et. al. mirror technique is also applicable to a separate measurement station process.
The preceding technique and many others relate only to the achievement of planarity regardless of the thickness of the remaining dielectric layer. The technological trend toward smaller device geometries has driven layer thicknesses to smaller dimensions. Thus, as CMP for planarization and etchback purposes continues to mature, the requirements put upon it become more demanding. Monitoring and end-point detection of planarity alone are no longer sufficient. Not only must planarity be achieved but also the layer must be further polished to meet a specified thickness. In some instances, a final thickness specification may take precedence over perfect planarity.